Zeroing In on Wi-Fi 7, Marvell Releases First 5 nm Multi-GB PHY Platform
The first chip based on Marvell's 5 nm multi-gigabit copper Ethernet PHY platform reduces PHY power by more than 50% and delivers up to 10 Gbps of bandwidth for Wi-Fi 7.
Marvell Technology has introduced its multi-gigabit (mGig) copper Ethernet PHY platform for the next generation of networking technologies. This announcement extends Marvell’s existing data infrastructure portfolio and adds more applications to the 5 nm platform.
As the number of end devices and Ethernet links increases, a high-performance and efficient Ethernet PHY offers compounding improvements for moving to/from the PHY layer. Image used courtesy of Marvell (Click to enlarge)
As designers move on from Wi-Fi 6/6E and begin targeting Wi-Fi 7, the bandwidth and power requirements make the design process a careful balancing act between raw performance and power efficiency. Marvell’s PHY platform, however, may give engineers the necessary edge to continue the momentum into newer Wi-Fi generations.
This article takes a closer look at Marvell's 5 nm technology platform and the first chip using the PHY platform to explore how the platform could enable better and faster communications.
Marvell Pushes Efficiency at 5 nm
Marvell's new PHY release is not the company's first 5 nm-based design. In fact, Marvell has collaborated with TSMC since 2020 to offer a more advanced data infrastructure portfolio. The announcement does, however, represent a major upgrade to Marvell’s offerings by adding support for mGig Ethernet PHY chips.
The move to a 5 nm process offers improved power performance, allowing for more efficient devices with less power dissipation. Image used courtesy of Marvell
The platform's preliminary results have shown a 50% power reduction in the PHY layer compared to previous generations while maintaining mGig performance. Especially in the context of Wi-Fi 7, this efficiency boost could have compounding effects as the number of links and access points increases.
Furthermore, the move to 5 nm will ultimately allow for more design flexibility as engineers take advantage of reduced thermal requirements to create smaller and more integrated chips. Although the PHY layer is only one component of the overall network, it plays a critical role in developing next-generation applications.
The Alaska M 3610 Ethernet Transceiver Chip
To validate the 5 nm platform’s performance, Marvell also introduced its Alaska M 3610 Ethernet PHY chip (data brief linked). The 3610 chip supports a single port at variable speeds up to 10 Gbps, while consuming less than 1 W of power. In addition to its performance vs. power consumption, the 3610 includes several other attractive features such as PTP, IEEE MAC security, and energy-efficiency Ethernet for designers looking to leverage PoE.
The Alaska M 3610 chip packs considerable functionality into a single chip, allowing improved performance and more dense integration without compromising power consumption. Image used courtesy of Marvell
The chip supports Category 6/6A cables with a minimum reach of 100 m in 10-G mode. This reach can be extended beyond 500 m using CAT 5e cables in conjunction with 100-M mode, making the 3610 a versatile chip for a variety of environments.
More Efficient Wi-Fi 7 Connectivity
For data throughput to steadily increase alongside the number of connected devices, both the performance and efficiency of every device in communications networks must follow suit. As such, the Marvell mGig Ethernet PHY platform is a step toward the adoption of Wi-Fi 7 in enterprise settings.
As the number of transceivers increases to accommodate more devices and complex architectures, designers can experiment with Marvell's chips and 5 nm platform to test its performance in both board-level and custom ASIC solutions.
